Lis3lv02dq.h
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This is drivers/spi/lis3lv02dq.h
#ifndef __LIS3LV02DQ_H__
#define __LIS3LV02DQ_H__
#define BIT(x) (1<<(x))
#define WHO_AM_I 0x0F /* address - default 0x3A */
#define I_AM_LIS3LV02DQ 0x3A
#define OFFSET_X 0x16 /* calibration */
#define OFFSET_Y 0x17 /* calibration */
#define OFFSET_Z 0x18 /* calibration */
#define GAIN_X 0x19 /* calibration */
#define GAIN_Y 0x1A /* calibration */
#define GAIN_Z 0x1B /* calibration */
#define CTRL_REG1 0x20 /* calibration */
/* power-down */
#define CTRL_REG1_PD (BIT(7) | BIT(6))
#define CTRL_REG1_PD_POWER_ON (BIT(7) | BIT(6))
#define CTRL_REG1_PD_POWER_OFF 0
/* decimation factor */
#define CTRL_REG1_DF (BIT(5) | BIT(4))
#define CTRL_REG1_DF_40_HZ 0
#define CTRL_REG1_DF_160_HZ BIT(4)
#define CTRL_REG1_DF_640_HZ BIT(5)
#define CTRL_REG1_DF_2560_HZ (BIT(5) | BIT(4))
#define CTRL_REG1_ST BIT(3) /* self-test */
#define CTRL_REG1_ZEN BIT(2) /* Z-axis enable */
#define CTRL_REG1_YEN BIT(1) /* Y-axis enable */
#define CTRL_REG1_XEN BIT(0) /* X-axis enable */
#define CTRL_REG2 0x21
#define CTRL_REG2_FS BIT(7) /* Full-Scale selection (0: ±2g; 1: ±6g) */
#define CTRL_REG2_BDU BIT(6) /* Block Data Update
* 0: continuous update
* 1: output registers not updated
* until MSB and LSB reading
*/
#define CTRL_REG2_BLE BIT(5) /* Big/Little (1/0) Endian selection */
#define CTRL_REG2_BOOT BIT(4) /* Reboot memory content */
#define CTRL_REG2_IEN BIT(3) /* Interrupt ENable
* 0: data ready on RDY pad
* 1: int req on RDY pad
*/
#define CTRL_REG2_DRDY BIT(2) /* Enable Data-Ready generation */
#define CTRL_REG2_SIM BIT(1) /* SPI Serial Interface Mode selection
* 0: 4-wire interface
* 1: 3-wire interface
*/
#define CTRL_REG2_DAS BIT(0) /* Data Alignment Selection
* 0: 12 bit right justified
* 1: 16 bit left justified
*/
#define CTRL_REG3 0x22
#define CTRL_REG3_ECK BIT(7) /* External Clock */
#define CTRL_REG3_HPDD BIT(6) /* High Pass filter enabled for Direction Detection */
#define CTRL_REG3_HPFF BIT(5) /* High Pass filter enabled for Free-Fall and Wake-Up */
#define CTRL_REG3_FDS BIT(4) /* Filtered Data Selection */
/* High-pass filter Cut-off Frequency Selection. Default value: 00 */
#define CTRL_REG3_CFS (BIT(1) | BIT(0))
#define CTRL_REG3_CFS_HPC_512 0
#define CTRL_REG3_CFS_HPC_1024 1
#define CTRL_REG3_CFS_HPC_2048 2
#define CTRL_REG3_CFS_HPC_4096 3
#define HP_FILTER_RESET 0x23
#define STATUS_REG 0x27
#define STATUS_REG_ZYXOR BIT(7) /* X, Y and Z axis Data Overrun */
#define STATUS_REG_ZOR BIT(6) /* Z axis Data Overrun */
#define STATUS_REG_YOR BIT(5) /* Y axis Data Overrun */
#define STATUS_REG_XOR BIT(4) /* X axis Data Overrun */
#define STATUS_REG_ZYXDA BIT(3) /* X, Y and Z axis new Data Available */
#define STATUS_REG_ZDA BIT(2) /* Z axis new Data Available */
#define STATUS_REG_YDA BIT(1) /* Y axis new Data Available */
#define STATUS_REG_XDA BIT(0) /* X axis new Data Available */
#define STATUS_REG_DA (STATUS_REG_XDA|STATUS_REG_YDA|STATUS_REG_ZDA)
#define STATUS_REG_OR (STATUS_REG_XOR|STATUS_REG_YOR|STATUS_REG_ZOR)
#define OUTX_L 0x28
#define OUTX_H 0x29
#define OUTY_L 0x2A
#define OUTY_H 0x2B
#define OUTZ_L 0x2C
#define OUTZ_H 0x2D
#define FF_WU_CFG 0x30 /* Free-fall and inertial wake-up configuration register */
#define FF_WU_CFG_AOI BIT(7) /* AND/OR (1/0) combination of Interrupt events interrupt request */
#define FF_WU_CFG_LIR BIT(6) /* Latch interrupt request */
#define FF_WU_CFG_ZHIE BIT(5) /* Enable Interrupt request on Z high */
#define FF_WU_CFG_ZLIE BIT(4) /* Enable Interrupt request on Z low */
#define FF_WU_CFG_YHIE BIT(3) /* Enable Interrupt request on Y high */
#define FF_WU_CFG_YLIE BIT(2) /* Enable Interrupt request on Y low */
#define FF_WU_CFG_XHIE BIT(1) /* Enable Interrupt request on X high */
#define FF_WU_CFG_XLIE BIT(0) /* Enable Interrupt request on X low */
#define FF_WU_SRC 0x31
#define FF_WU_SRC_IA BIT(6) /* Interrupt Active */
#define FF_WU_SRC_ZH BIT(5) /* Z High */
#define FF_WU_SRC_ZL BIT(4) /* Z Low */
#define FF_WU_SRC_YH BIT(3) /* Y High */
#define FF_WU_SRC_YL BIT(2) /* Y Low */
#define FF_WU_SRC_XH BIT(1) /* X High */
#define FF_WU_SRC_XL BIT(0) /* X Low */
#define FF_WU_ACK 0x32
#define FF_WU_THS_L 0x34 /* Free-fall / Inertial Wake Up Acceleration Threshold */
#define FF_WU_THS_H 0x35
#define FF_WU_DURATION 0x36
#define DD_CFG 0x38 /* Direction-detector configuration register */
#define DD_CFG_IEND BIT(7) /* Interrupt enable on Direction change */
#define DD_CFG_LIR BIT(6) /* Latch Interrupt request into DD_SRC reg */
#define DD_CFG_ZHIE BIT(5) /* Enable interrupt generation on Z high */
#define DD_CFG_ZLIE BIT(4) /* Enable interrupt generation on Z low */
#define DD_CFG_YHIE BIT(3) /* Enable interrupt generation on Y high */
#define DD_CFG_YLIE BIT(2) /* Enable interrupt generation on Y low */
#define DD_CFG_XHIE BIT(1) /* Enable interrupt generation on X high */
#define DD_CFG_XLIE BIT(0) /* Enable interrupt generation on X low */
#define DD_SRC 0x39 /* Direction detector source register */
#define DD_SRC_IA BIT(7) /* Interrupt event from direction change */
#define DD_SRC_ZH BIT(6) /* Z High */
#define DD_SRC_ZL BIT(5) /* Z Low */
#define DD_SRC_YH BIT(3) /* Y High */
#define DD_SRC_YL BIT(2) /* Y Low */
#define DD_SRC_XH BIT(1) /* X High */
#define DD_SRC_XL BIT(0) /* X Low */
#define DD_ACK 0x3A
#define DD_THSI_L 0x3C /* Direction detection Internal Threshold */
#define DD_THSI_H 0x3D
#define DD_THSE_L 0x3E /* Direction detection External Threshold */
#define DD_THSE_H 0x3F
#endif // __LIS3LV02DQ_H__
#ifndef DECL_BEGIN
#define DECL_BEGIN
#endif
#ifndef DECL_REG
#define DECL_REG(a,b,c)
#endif
#ifndef DECL_RE_
#define DECL_RE_(a,b,c)
#endif
#ifndef DECL_END
#define DECL_END
#endif
DECL_BEGIN
DECL_REG(WHO_AM_I, 0xFF, "i2c address")
DECL_REG(OFFSET_X, 0xFF, "digital offset trimming for x axis")
DECL_REG(OFFSET_Y, 0xFF, "digital offset trimming for y axis")
DECL_REG(OFFSET_Z, 0xFF, "digital offset trimming for z axis")
DECL_REG(GAIN_X, 0xFF, "digital gain trimming for x axis")
DECL_REG(GAIN_Y, 0xFF, "digital gain trimming for y axis")
DECL_REG(GAIN_Z, 0xFF, "digital gain trimming for z axis")
DECL_REG(CTRL_REG1, 0xFF, "control register 1")
DECL_RE_(CTRL_REG1, CTRL_REG1_PD, "power-down")
DECL_RE_(CTRL_REG1, CTRL_REG1_DF, "decimation factor")
DECL_RE_(CTRL_REG1, CTRL_REG1_ST, "self-test")
DECL_RE_(CTRL_REG1, CTRL_REG1_ZEN, "z axis enable")
DECL_RE_(CTRL_REG1, CTRL_REG1_YEN, "y axis enable")
DECL_RE_(CTRL_REG1, CTRL_REG1_XEN, "x axis enable")
DECL_REG(CTRL_REG2, 0xFF, "control register 2")
DECL_RE_(CTRL_REG2, CTRL_REG2_FS, "full-scale selection (0/1 +-2/6g)")
DECL_RE_(CTRL_REG2, CTRL_REG2_BDU, "block data update")
DECL_RE_(CTRL_REG2, CTRL_REG2_BLE, "big/little (1/0) endian selection")
DECL_RE_(CTRL_REG2, CTRL_REG2_BOOT, "reboot memory content")
DECL_RE_(CTRL_REG2, CTRL_REG2_IEN, "interrupt enable")
DECL_RE_(CTRL_REG2, CTRL_REG2_DRDY, "enable data-ready generation")
DECL_RE_(CTRL_REG2, CTRL_REG2_SIM, "spi serial interface mode selection")
DECL_RE_(CTRL_REG2, CTRL_REG2_DAS, "data alignment selection")
DECL_REG(CTRL_REG3, 0xFF, "control register 3")
DECL_RE_(CTRL_REG3, CTRL_REG3_ECK, "external clock")
DECL_RE_(CTRL_REG3, CTRL_REG3_HPDD, "high pass filter enabled for direction detection")
DECL_RE_(CTRL_REG3, CTRL_REG3_HPFF, "high pass filter enabled for free-fall and wake-up")
DECL_RE_(CTRL_REG3, CTRL_REG3_FDS, "filtered data selection")
DECL_RE_(CTRL_REG3, CTRL_REG3_CFS, "high-pass filter cut-off frequency selection")
DECL_REG(HP_FILTER_RESET, 0xFF, "hight-pass filter reset")
DECL_REG(STATUS_REG, 0xFF, "status register")
DECL_RE_(STATUS_REG, STATUS_REG_ZYXOR, "x, y and z axis data overrun")
DECL_RE_(STATUS_REG, STATUS_REG_ZOR, "z axis data overrun")
DECL_RE_(STATUS_REG, STATUS_REG_YOR, "y axis data overrun")
DECL_RE_(STATUS_REG, STATUS_REG_XOR, "x axis data overrun")
DECL_RE_(STATUS_REG, STATUS_REG_ZYXDA, "x, y and z axis new data available")
DECL_RE_(STATUS_REG, STATUS_REG_ZDA, "z axis new data available")
DECL_RE_(STATUS_REG, STATUS_REG_YDA, "y axis new data available")
DECL_RE_(STATUS_REG, STATUS_REG_XDA, "x axis new data available")
DECL_REG(OUTX_L, 0xFF, "x axis acceleration data LSB")
DECL_REG(OUTX_H, 0xFF, "x axis acceleration data MSB")
DECL_REG(OUTY_L, 0xFF, "y axis acceleration data LSB")
DECL_REG(OUTY_H, 0xFF, "y axis acceleration data MSB")
DECL_REG(OUTZ_L, 0xFF, "z axis acceleration data LSB")
DECL_REG(OUTZ_H, 0xFF, "z axis acceleration data MSB")
DECL_REG(FF_WU_CFG,0xFF,"free-fall and inertial wake-up configuration register")
DECL_RE_(FF_WU_CFG, FF_WU_CFG_AOI, "and/or (1/0) combination of interrupt events interrupt request")
DECL_RE_(FF_WU_CFG, FF_WU_CFG_LIR, "latch interrupt request")
DECL_RE_(FF_WU_CFG, FF_WU_CFG_ZHIE, "enable interrupt request on z high")
DECL_RE_(FF_WU_CFG, FF_WU_CFG_ZLIE, "enable interrupt request on z low")
DECL_RE_(FF_WU_CFG, FF_WU_CFG_YHIE, "enable interrupt request on y high")
DECL_RE_(FF_WU_CFG, FF_WU_CFG_YLIE, "enable interrupt request on y low")
DECL_RE_(FF_WU_CFG, FF_WU_CFG_XHIE, "enable interrupt request on x high")
DECL_RE_(FF_WU_CFG, FF_WU_CFG_XLIE, "enable interrupt request on x low")
DECL_REG(FF_WU_SRC, 0xFF, "wake-up interrupt source configuration")
DECL_RE_(FF_WU_SRC, FF_WU_SRC_IA, "interrupt active")
DECL_RE_(FF_WU_SRC, FF_WU_SRC_ZH, "z high")
DECL_RE_(FF_WU_SRC, FF_WU_SRC_ZL, "z low")
DECL_RE_(FF_WU_SRC, FF_WU_SRC_YH, "y high")
DECL_RE_(FF_WU_SRC, FF_WU_SRC_YL, "y low")
DECL_RE_(FF_WU_SRC, FF_WU_SRC_XH, "x high")
DECL_RE_(FF_WU_SRC, FF_WU_SRC_XL, "x low")
DECL_REG(FF_WU_ACK, 0xFF, "wake-up ack")
DECL_REG(FF_WU_THS_L, 0xFF, "free-fall/inertial wake up acceleration threshold LSB")
DECL_REG(FF_WU_THS_H, 0xFF, "free-fall/inertial wake up acceleration threshold MSB")
DECL_REG(FF_WU_DURATION,0xFF, "min recognized free-fall duration")
DECL_REG(DD_CFG, 0xFF, "direction-detector configuration register")
DECL_RE_(DD_CFG, DD_CFG_IEND, "interrupt enable on direction change")
DECL_RE_(DD_CFG, DD_CFG_LIR , "latch interrupt request into DD_SRC reg")
DECL_RE_(DD_CFG, DD_CFG_ZHIE, "enable interrupt generation on z high")
DECL_RE_(DD_CFG, DD_CFG_ZLIE, "enable interrupt generation on z low")
DECL_RE_(DD_CFG, DD_CFG_YHIE, "enable interrupt generation on y high")
DECL_RE_(DD_CFG, DD_CFG_YLIE, "enable interrupt generation on y low")
DECL_RE_(DD_CFG, DD_CFG_XHIE, "enable interrupt generation on x high")
DECL_RE_(DD_CFG, DD_CFG_XLIE, "enable interrupt generation on x low")
DECL_REG(DD_SRC, 0xFF, "direction detector source register")
DECL_RE_(DD_SRC, DD_SRC_IA, "interrupt event from direction change")
DECL_RE_(DD_SRC, DD_SRC_ZH, "z high")
DECL_RE_(DD_SRC, DD_SRC_ZL, "z low")
DECL_RE_(DD_SRC, DD_SRC_YH, "y high")
DECL_RE_(DD_SRC, DD_SRC_YL, "y low")
DECL_RE_(DD_SRC, DD_SRC_XH, "x high")
DECL_RE_(DD_SRC, DD_SRC_XL, "x low")
DECL_REG(DD_ACK, 0xFF, "direction detection ack")
DECL_REG(DD_THSI_L, 0xFF, "direction detection internal threshold LSB")
DECL_REG(DD_THSI_H, 0xFF, "direction detection internal threshold MSB")
DECL_REG(DD_THSE_L, 0xFF, "direction detection external threshold LSB")
DECL_REG(DD_THSE_H, 0xFF, "direction detection external threshold MSB")
DECL_END
#undef DECL_RE_
#undef DECL_REG
#undef DECL_END
#undef DECL_BEGIN
